1. FIELD OF THE INVENTION
This invention relates to the field of multiplexed DRAM input/output systems that allow for high bandwidth CPU operation.
2. BACKGROUND ART
A typical computer system consists of a number of modules or components. Computer systems typically include a central processing unit (CPU) such as a microprocessor. The microprocessor is a program-controlled device that obtains, decodes and executes instructions. A computer system also includes program storage components for storing program instructions, and data storage components for storing data. These storage components may be read only memory (ROM), random access memory (RAM), disk or tape storage, or any other suitable storage means.
A computer system typically also includes input/output (I/O) components for connecting external devices to the microprocessor. Special purpose components, such as memory management units or co-processors, may also be part of the computer system.
The memory component, also known as a "main memory," is a scarce resource that is dynamically allocated to users, programs or processes. Main memory is typically a silicon-based memory such as a RAM. In many applications, dynamic random access memory (DRAM) is used as the main memory. Processor main memory is "byte" organized. That is, memory is arranged as a sequence of 8-bit bytes and the byte is the smallest unit of information accessed out of the memory. In one convention, an entire row is selected by a row address and columns are accessed in groups of 8 bits. In some implementations, 16-bit words (2 bytes) or 32-bit words (4 bytes) are accessed at one time.
A block diagram of a memory module is illustrated in FIG. 1. The memory module is generally indicated by the elements within boundary 101. The memory module 101 comprises a row select decoder 102 coupled to a memory array 103. A column select decoder 107 is coupled through column input/output circuits 105 to memory array 103. Column input/output circuits 105 receive input data control signals from input data control block 104 and provides data to output buffers 106. A control logic block 108 provides a read signal 112 to output buffers block 106. Row address bus lines A.sub.0 -A.sub.i-1 are coupled to row select decoder block 102. The row select decoder block 102 interprets the information on the address bus lines A.sub.0 -A.sub.i-1 so that the appropriate row of memory array 103 can be selected. The memory array 103 comprises a plurality of memory elements arranged in rows and columns.
Column addresses are provided on address bus lines A.sub.i -A.sub.N-1. These addresses are provided to column select decoder block 107. Column select decoder block 107 interprets the address information and provides a column select signal to the column input/output circuits 105. The column input/output circuits 105 provide the column select signal to the memory array 103 so that the appropriate column groups can be selected.
The memory module 101 also includes a control logic block 108 that receives read, write and CS signals. When the control logic block receives a write command, it enables input data control block 104 to receive data from data bus lines 110. The input data control block 104 provides the data to column input/output circuit 105 which can then write it into the memory array 103 at appropriate column and row locations. For read operations, the control logic block 108 provides a read signal 112 to output buffers 106. Information is read from memory array 103 and provided by column input/output circuits block 105 to output buffers 106 and eventually to data output lines 111. In many implementations, the data bus lines 110 are shared with the data output lines 111.
In the case of dynamic random access memories, periodic refreshing is required so that the storage contents can be maintained. Memory refreshing may be done either by the CPU or by an external refresh controller. Memory refreshing can be completely transparent (that is, done during gaps in the CPU timing) or partially transparent, (by inserting a refresh cycle after a "next instruction fetch" cycle). Refreshing is accomplished by applying current to capacitors associated with each memory cell.
It is often desired to expand the amount of main memory that can be accessed by a processor or CPU. One method of increasing available addressable memory is known as "bank switching." In a bank switching scheme, main memory consists of a number of separate physical memory blocks or memory banks. Consider the situation where a microprocessor or CPU issues an N-bit address. Each memory bank then consists of 2.sup.N contiguously addressed physical locations numbered from zero to 2.sup.N-1. In a bank switching scheme, one bank of memory is enabled while all other banks remain disabled. Bank selector logic, under the control of an appropriate supervisor program, selects one of the memory banks to receive the CPU address.
To access the memory, a CPU or I/O controller must assert an address on all banks and assert the output enable on the one bank in which the desired data is stored. Unfortunately, this has the disadvantage of being slower than true multiplexing of memory banks, due to the long turn-on and turn-off time of DRAM output enable, and of presenting the capacitive loads of all of the banks onto the same data bus wires.
Another aspect common in DRAM memory systems is the provision of error correction for protecting against data errors when reading from memory. Error correction code (ECC) is a standard, widely-implemented data protection function, often used for magnetic media. Prior art implementations of ECC as well as prior art means for accessing the DRAM memory, however, have not supported the full utilization of the memory bandwidth.
A number of memory management schemes are described in the prior art. For example, U.S. Pat. No. 4,901,230 to Chen, et al., describes a multiprocessing system implementing two processors in a shared register section. Each processor has several parallel ports to the main memory. Chen, et al., makes use of buffer registers (674-681) and multiplexers (690-691) to output data to the memory. Although multiprocessing is supported, no extra circuitry is described which would enhance the DRAM bandwidth.
Sundet, U.S. Pat. No. 4,630,230, describes an add-on storage system. The system of Sundet attempts to minimize fan in, fan out and addressing requirements by organizing the storage into a plurality of sections. The memory address is supplied to all sections and then data words are passed in and out in a serial fashion from section to section using registers. In a read operation, each section outputs a word to its register simultaneously, then transfers the word from section to section out to the port. In a write operation, the opposite transaction takes place.
Amitai, U.S. Pat. No. 4,797,850, describes a dynamic random access memory controller with multiple independent control channels. The memory controller is used to create address strobe signals to access individual bytes of memory out of the DRAM.
Halford, U.S. Pat. No. 4,807,121, is directed to a peripheral interface system having an input-output processor (IOP) including a RAM memory, provided to perform certain input-output tasks for a CPU. The system further includes a multiplexer which multiplexes data between an IOP DMA (direct memory access) port and up to four disk controller units and two data buffers, respectively. Data is transferred between the multiplexer and the local memory in groups of four parcels, with each group associated with a lone channel.
Shinoda, et al., U.S. Pat. No. 4,912,679, describes a buffered addressing system that adjusts the processor address rate to the relatively slow memory address rate. With this system, the processor itself does not have to compensate for the slow speed of the memory addressing and thus can operate at a much more efficient rate.
From, et al., U.S. Pat. No. 4,951,246, is directed to a pipelined group storage system. A nibble mode DRAM is deployed in a plurality of memory banks and addressing circuitry is adapted to address the DRAM in nibble mode cycles from a plurality of ports.